1. Field of the Invention
The present invention relates to a microprocessor, and more specifically to a data transfer structure of a microprocessor capable of complying with a plurality of different data bus widths.
2. Description of Related Art
In a data processing system using a microprocessor, processing performance is influenced by a bit width of a data bus for transferring data between the microprocessor and a memory which stores instruction codes and operands.
A data width is typified by, for example, 8 bits, 16 bits, and 32 bits, which are a power of 2. If a large data bus width is adopted, data transfer capacity can be increased. Therefore, the large data bus width is very convenient in an application having a large number of opportunities of handling data of a wide width.
However, the increase of the data bus width is accompanied by following disadvantages:
(1) The minimum constituting unit of a memory is increased:
For example, if a dynamic RAM (random access memory) chip of 8 bits.times.128K words is used, a memory of one minimum construction can be constituted of only one RAM chip in the case of a 8-bit bus. In the case of a 16-bit bus, on the other hand, two RAM chips are required to constitute a memory of one minimum construction. If a required memory capacity is 128 Kbytes, the latter case is equipped with a wasteful memory capacity of 128 Kbytes. Namely, a memory system having a wide bus width often has the above mentioned wasteful area (which is generally called a "fragmentation").
(2) A wiring zone is increased:
If a wide bus width is adopted, the number of wiring conductors for physically connecting a data bus between the microprocessor and the memory system is increased. Since parts such as LSI (large scale integrated) chips or other components cannot be located on wiring conductor patterns foraged on a printed circuit board, the overall size of the system is inevitably increased.
(3) The number of dam buffers is increased:
A large driving power for driving a data bus connected between the microprocessor and the memory system is required in view of the current, electrostatic capacitance and noise. On the other hand, since buffers having a large capacity for driving the data bus cannot be internally assembled in the microprocessor or in the memory chip, it is necessary to externally provide an integrated circuit for data buffers. These data buffers have not only a high driving power, but also a large electric power consumption. Therefore, it becomes a large cause of heat generation in the overall system, and an electric power source having an increased capacity becomes necessary.
Under the above mentioned circumstance, it is desired to increase the data bus width in order to elevate performance, even if the above mentioned disadvantages are encountered. In this case, it is desired to increase the data bus width, without rewriting software.
Microprocessors, which have the same architecture in register sets, instruction sets, instruction codes, etc, but which have different data bus widths, have been proposed. For example, 8/16-bits microprocessors V20/V30 available from NEC Corporation have the same architecture and are so configured that internal processing is performed with 16 bits. However, the V20 microprocessor has a data bus terminal of 8 bits, and V30 microprocessor has a data bus terminal of 16 bits. Since there is a difference in data transfer capacity because of the difference in the bus width, the V20 and V30 microprocessors have different capacities of an instruction prefetch buffer. The microprocessor has 4 bytes, and the V30 microprocessor has 6 bytes. In addition, the construction and the operation for the instruction execution and the instruction decoding are the same, but there is a difference in the bus control circuit for controlling the data bus and in the terminal function.
As mentioned above, since the V20 and V30 microprocessors have the same architecture, a program operating in one of the microprocessor can operate in the other microprocessor. But, the V20 and V30 microprocessors are different in performance, which are attributable to only to a difference in the number of clocks. Specifically, the V30 microprocessor has a maximum data transfer capacity which is double that of the V20 microprocessor and has an average performance which is 1.3 times to 1.5 times that of the V20 microprocessor. Accordingly, a user can select one of the V20 and V30 microprocessors from a total consideration of a required system performance and a required total cost.
On the other hand, a 32-bit microprocessor i80486 available from Intel Corp. can be coupled with data buses having different bus widths. This microprocessor has data of 8/16/32 bits for basic operation, but has an external data bus terminal of 32 bits. An external access of 8 bits and 16 bits is performed by dividing the external data bus of 32 bits into four 8-bit units of 8 bits and by selectively utilizing one or two of the four units.
In addition, the i80486 microprocessor has a 30-bit address terminal of A31 to A2 for designating an address for an external memory. This address indicates an address for the 32-bit (word) data, but it does not indicate an address for the 16-bit (half word) data or the 8-bit (byte) data. In order to transfer data between the microprocessor and the external memory, the microprocessor has a 32-bit data bus terminal of D31 to D0, which is divided into four 8-bit units for convenience of explanation. Here, the four 8-bit units are called B3(D31-D24), B2(D23-D16), B1(D15-D8) and B0(D7-D0).
Furthermore, the microprocessor has four output terminals BE3(-) to BE0(-) for indicating which of the four 8-bit units is to be used for the data transfer. Here, the parenthesized minus indicates a negative logic. The BE3(-) terminal indicates that data is transferred by using the 8-bit unit B3 of the data bus terminal. Similarly, the BE2(-) terminal corresponds to the 8-bit unit B2 of the data bus terminal, and the BE1(-) terminal and the BE0(-) terminal correspond to the 8-bit unit B1 and the 8-bit unit B0 of the data bus terminal, respectively.
For example, assuming that data of 16 bits is transferred between the microprocessor mid an address "No. 1" of a memory, "00000001.sub.h " for the 32-bit data is outputted from the address terminal, and "0011.sub.h " for indicating effectiveness of the data bus is outputted to the BE3(-) to BEO(-) terminals. Here, the subscript "h" indicates a hexadecimal notation, and the subscript "b" shows a binary notation. Thus, in the case of reading, 32-bit data on the address "No. 1" of the external memory is accessed, and 16-bit data is transferred to the microprocessor through the 8-bit units B3 and B2 of the data bus terminal. In the case of writing, 16-bit data is transferred from the microprocessor to the 8-bit units B3 and B2 of the data bus terminal, and then to the external memory.
In the i80486 microprocessor, the most significant 16 bits (B3 and B2) of the data bus terminal is used in the following cases:
(1) 32-bit data is accessed. PA1 (2) 16-bit data having the least significant two bits other than "00.sub.b " is accessed. PA1 (3) 8-bit data having the least significant two bits other than "0X.sub.b " is accessed (where "X" shows an indefinite value). PA1 (1) 32-bit data having the least significant two bits of "00.sub.b " is accessed. PA1 (2) 16-bit data having the least significant two bits other than "11.sub.b " is accessed.
In addition, only one bus cycle is perforated in the following eases:
Therefore, the i80486 microprocessor cannot be coupled to an external memory having a 16-bit width, by using only the least significant 16 bits D15 to D0 of the data bus terminal D32 to D0.
In order to solve this problem, the i-80486 microprocessor is provided with a BS16(-) terminal for the data transfer by the 16-bit width data bus and a BS8(-) terminal for the data transfer by the 8-bit width data bus. If one of these terminals is activated in a bus cycle, data can be transferred by using only the least significant 16 bits (B1 and B0) of the data bus terminal or only the least significant 8 bits (B0) of the data bus terminal.
Here, for simplification of explanation, the data transfer using the 16-bit width data bus by activating the BS16(-) terminal will be explained. Similarly to the above case, assume that data of 16 bits is transferred between the microprocessor and an address "No. 1" of a memory.
Under the precondition that the 32-bit bus can be used, the i80486 microprocessor outputs the most significant 8 bits and the least significant 8 bits of the 16-bit data to the 8-bit units B2 and B1 of the data bus terminal. On the other-hand, "1001.sub.b " is outputted to the BE3(-) to BE0(-) terminals.
Before the completion of the bus cycle, if the i80486 microprocessor detects that the BS16(-) terminal is in activated condition, one bus cycle is succeedingly added. In this additional bus cycle, "1011.sub.b " is outputted to the BE3(-) to BE0(-) terminals. The most significant 8 bits of the 16-bit data is outputted to the 8-bit unit B2 of the data bus terminal.
As seen from the above, the least significant 8 bits of the 16-bit data is transferred in the first bus cycle and the most significant 8 bits of the 16-bit data is transferred in the second and additional bus cycle.
The above mentioned method in which after the bus cycle is started, an external condition (the status of the BS16(-) terminal) is detected, and a bus cycle is added on the basis of the result of the detection so that data is transferred to a data bus having a narrow bit width, is called a "dynamic bus-sizing function".
However, when data having different bit widths (for example, 8/16/32 bits) is transferred by coupling to data buses of different bit widths (for example, a fixed 32-bit width and a fixed 16-bit width), the following problems have been encountered:
(1) The power consumption is large:
Referring to the above mentioned example, in the first bus cycle, invalid 8-bit data is driven to the 8-bit units B3 and B0 of the 32-bit data bus terminal, and 8-bit data that is not actually transferred is driven to the 8-bit unit B2 of the 32-bit data bus terminal. In the second bus cycle, invalid 8-bit data is driven to the 8-bit units B3, B1 and B0 of the 32-bit data bus terminal. Thus, since the opportunity of driving the data bus terminal portion which is not used for the actual data transfer is increased, and therefore, a wasteful power consumption occurs.
(2) The number of external circuits is increased:
Buffers are required to selectively couple the data bus terminal of the microprocessor with the external data bus in units of 8 bits. In the above mentioned example the four 8-bit units B3(D31-D24), B2(D23-D16), B1(D15-D8) and B0(D7-D0) of the 32-bit data bus terminal of the microprocessor are connected through four external data bus buffers to the data bus. The reason for this is that, in the dynamic bus-sizing system, since the bit width of the data bus is detected at the first place after the bus cycle is started, data is transferred in the first bus cycle, assuming the maximum bit width (for example 32 bits).